The escalating demand for telecommunications bandwidth has placed a strain on existing service delivery infrastructure and created a desire for faster and more efficient data delivery networks. The principal elements in a switched data network which determine the bandwidth capacity are the switching nodes. Many switching node architectures have been invented for efficiently switching data packets at high speeds. Data packet switching nodes have been traditionally constructed with equal ingress and egress capacities and with symmetrical ingress/egress port configurations. A symmetrical configuration is suitable if the capacity requirement of the connection to each port is identical in opposite directions. In a modern multiservice network, however, a connection may have vastly different data rates in opposite directions. For example, the connection from a user to a database may have a data rate of about 1 kb/s, whereas the connection from the database to the user may require 100 kb/s, or more. If such asymmetry is permanent, the user may be connected to the network by asymmetrical outbound and inbound links. If the asymmetry is time-variant, however, the links connecting the user to the network must be of a sufficiently high capacity to accommodate the peak rates in both directions.
Of the many data packet switch architectures that have been invented, one of the most widely used is the common-memory (CM) switch. This type of switch is widely used in data packet networks, such as ATM networks for example. In a CM switch, the switch capacity is limited by the CM access speed. In a non-blocking CM implementation, the sum of the port capacities (expressed in bits per second) is less than, or equal to, the capacity of the CM. In such switches, the ports normally access the CM in a sequential cycle, each port being given an equal time window in which to write packets to, or read packets from, the CM. This often results in idle periods when ports have no payload packets to write to, or read from, the CM. Any idle capacity resulting from port under-utilization cannot be recovered if the ports access the CM for a fixed period of time in each access cycle.
Asymmetrical unicast connections such as the one described above place traffic loads on the ingress and egress sides of a port which may differ significantly, but the total ingress rate of all input ports is always equal to the total egress rate of all output ports. In modern multiservice networks, multicasting is frequently required. Multicasting involves switching data from one input source to a plurality of outputs. When multicasting occurs, however, not only are the connection bit rates naturally asymmetrical, but the total egress rate may substantially exceed the total ingress rate. Therefore, switching multicast traffic using a symmetrical switch results in unavoidable core capacity wastage.
There therefore exists a need for an effective method of control port access to the common-memory in CM switches to maximize core utilization and switch throughput. There also exists a need for a CM switch architecture for efficiently switching unbalanced unicast traffic loads using an asymmetrical port access capacity. There further exists a need for a CM switch architecture which is especially adapted for multicasting to ensure that valuable core resources are efficiently utilized in network applications where multicasting is consistently required.